The present invention relates generally to jitter generators and more particularly to circuits and methods for intentionally inducing desired amounts of jitter to the edges of pulses of a pulse train for use for testing a device under test.
Digital signals provided to digital circuitry are not always in an ideal condition with noise in the digital signal producing jitter. Therefore, digital circuits are required to be able to operate in the presence of jitter in the digital signal, or pulse train. It is also important to test digital circuits during development using digital test signals or pulse trains that include jitter. This test is called jitter tolerance test.
A jitter test signal may be generated by inducing jitter to a stable digital test signal, called a reference pulse train hereafter. The reference pulse train and the jitter pulse train are provided to a digital circuit and would allow for a comparison test between the stable reference pulse train and the jitter pulse train. To induce jitter to the edges of the pulses in the reference pulse train, the edges are delayed and the delay time is varied.
FIG. 1 shows a block diagram disclosed in Japanese patent publication No. 7-95022 (non-examined) of a prior art circuit for delaying the rising edge and/or the falling edge of a pulse provided to the circuit. A buffer 1 receives an input pulse train and provides non-inverted and inverted outputs to delay circuits 2 and 3 respectively. First and second delay setup signals are provided to the delay circuits 2 and 3 to independently set delay times td1 and td2 respectively. An AND gate 4 receives the output of the delay circuit 2 and the non-inverted output of the buffer 1 and provides a logical product to the set input terminal S of an SR flip-flop 6. An AND gate 5 receives the output of the delay circuit 3 and the inverted output of the buffer 1 and provides a logical product to the reset input terminal R of the SR flip-flop 6. Therefore, the timing of the rising edge of the SR flip-flop 6 is determined by the input signal to the S input terminal of the SR flip-flop 6, and timing of the falling edge is determined by the input signal to the R input terminal.
FIG. 2 shows a timing chart of the circuit illustrated in the block diagram in FIG. 1. The AND gate 4 generates a rising edge in response to the delayed rising edge from the delay circuit 2 at time td1 after the rising edge t1 of an input pulse, which decides the rising edge of the output of the RS flip-flop 6. Similarly, the AND gate 5 generates a rising edge in response to the delayed rising edge from the delay circuit 3 at time td2 after the falling edge t2 of the input pulse, which decides the falling edge of the output of the RS flip-flop 6.
The Japanese patent publication No. 7-95022 also discloses a specific example of an analog delay circuit usable for the delay circuits 2 and 3, which compares a variable reference voltage with a ramp waveform for changing the delay time. It is desirable that the delay time is accurate according to a user setting and adaptable to wide bandwidths of the input pulse. However, it is difficult for this analog method to produce a linear ramp waveform for high frequencies so it is difficult to get an accurate delay time for the high frequencies. In addition, random jitter in the comparator makes it difficult to produce small amounts of accurate delay time.
The Japanese patent publication No. 7-95022 further discloses a digital delay circuit that changes the delay time by selectively connecting a plurality of delay elements. The digital delay elements have a fixed delay time, which provides an accurate delay time for wide frequencies of an input pulse train. Further, higher resolution and wider delay time selection may be achieved by providing a large number of delay elements having shorter delay. FIG. 3 shows an equivalent block diagram of the digital delay circuit that has four delay lines DLs and four connection lines SLs, which are selectively cascaded by switches SWs to control the total delay time. The delay lines DLs have their own fixed delay time respectively and the connection lines SLs have no delay time.
U.S. Pat. No. 6,127,871 (corresponding to EP-A-853385) also discloses a digital delay circuit. Variable delay cells are cascaded to get a wide variable range of the delay time. U.S. patent application publication No. 2003/0041294 A1 discloses jitter generation using a digital delay unit.
One could use an output signal from an IC package as the reference pulse train. However, this would require many ICs to generate the many kinds of pulse trains. An arbitrary pulse train generator has been developed, which stores the data of the pulse trains to generate the real signals. Japanese patent publication No. 7-97130 (examined) discloses an example of the arbitrary pulse train generator.
A digital delay circuit as shown in FIG. 3 can provide an accurate delay time, but develops problems if the delay time is changed dynamically. That is, if a delay time is shorter than the following one, the former input pulse remains in one of the delay lines DLs and the later pulse reaches the output terminal of the last delay line faster so that the order of the input pulses may change or some pulses may mix at the output terminal. Thus, this type of digital delay circuit has shortcomings for jitter generation.
Referring to FIGS. 1 and 2, if the delay time td1 of the first delay circuit 2 is shorter than the pulse width Pw1 from the point t1 to t2, the output of the AND gate 4 has a rising edge. But if the delay time td1 of the first delay circuit 2 is longer than the pulse width Pw1, such as td3 of FIG. 2i, the output of the AND gate 4 has no rising edge because the logical product between the outputs of the first delay circuit 2 and the buffer 2 is low. That is, even if the delay time td3 is set to the first delay circuit 2, it does not produce a rising edge at the output of the SR flip-flop. This is similar to a falling edge case.
Accordingly, what is desired is to induce jitter to the rising and/or falling edges of pulses in a reference pulse train according to a user request. To induce the desired jitter to the edges, the delay time applied to the reference pulse train is varied continuously and controlled accurately. In addition, the present invention can provide a pulse train in which some of the pulses have jitter and others do not have jitter.